1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a command latency circuit for a programmable SynchLink Dynamic Random Access Memory (hereinafter, referred to as `SLDRAM`) which is an ultrahigh speed memory device, and a latency control method therefor.
2. Description of the Background Art
As the high integration of a semiconductor memory device has been rapidly achieved, the ultrahigh speed thereof has also proceeded. Especially, the SLDRAM achieving the ultrahigh speed has been recently developed.
The SLDRAM is a kind of Dynamic Random Access Memory (hereinafter, referred to as `DRAM`), and has a ultrahigh speed performance superior to a conventional synchronous DRAM. Especially, the SLDRAM is operated at a rising edge and a falling edge of a clock, and thus has a considerably high data bandwidth. Firstly, command signals (namely, /RAS, /CAS, /WE, etc.) and address signals which are necessary to perform a DRAM operation are inputted to the SLDRAM as a single packet four times, having a total width of 40 bits, through pins of 10 bits which are command addresses. The SLDRAM carries out the general DRAM operations (read, write, etc.) and the other specific operations by decoding the command address of 40 bits. The SLDRAM performs a bank read/write operation and a page read/write operation, and is operated at burst 4 or burst 8. In addition, during the read/write operation, the SLDRAM can adjust a time of transmitting/receiving a data to/from a controller by using an internally-stored register value. The register value can be programmed to have an appropriate value by the controller.
On the other hand, the conventional SLDRAM utilizes a master clock in a write command latency. Accordingly, there is not provided a specific logic structure for controlling the bank write operation. As a result, a write command latency circuit is operated in other operations, besides the bank write operation (for example, read latency), thereby increasing the power consumption. In addition, loading of the master clock is remarkably increased. Furthermore, many shift registers are required to delay a write command, and thus disadvantageously occupy a large area in the device.